The new Timing Table Editor for DDR2 SPD has been developed. It has an in-depth interface design implementation that allows editing all the necessary memory timings of SPD intuitively.
Every editing tool now has a navigation bar in one color style and minimum set of control buttons. The color of the navigation bar is customized in the Settings menu.
The procedure for analyzing Part Numbers of memory modules now supports the DDR4 Part Numbering system of Smart Modular. This helps to determine DRAM Manufacturer and DRAM Die if these two required parameters were not programmed in SPD.
To comply with the “JEDEC SPD for DDR4 Release 3 Annex” the Timing Table Editor sets the Maximum DRAM Cycle Time to 1.6 ns (625 MHz) for every preset of the JEDEC standard speed bin list.
The SPDWD Patch Assistant enables to select the PCIEXBAR address from the list, which is filled with the three base addresses being most typical for the Intel platform.
Added description for all the SPD bytes of DDR4 LRDIMM being displayed on the Statusbar.
SPD release dates of DDR4 DRAM modules have been revised.
The “Product Details” Editor sets the Odd Parity bit in all the Manufacturer ID Codes to meet JEDEC requirements.
Added SMBus Controller Device ID of Intel Gemini Lake code-named SOCs to enable accessing SPD EEPROM.
The part marking of Hynix DDR2 SDRAM components, mounted on the third-party DRAM modules, is determined.
The full report includes detailed information specific to hybrid DDR4 NVDIMM modules.
The SPD Browser enables to fetch SPD dumps from the SPD database by “NVDIMM” module type.
Fixed a bug due to the Register Manufacturer and Register Model fields not being displayed for DDR4 NVRDIMM and DDR4 LRDIMM.
Fixed a bug due SPD data not being decoded when opening the SPD dump from the database if the “Add to shortcuts” button has been pressed before.
Fixed “Division by zero” error due to SPD reporting not being possible for certain DRAM module manufacturers.